Interfacing and testing ROM chips – Part 2

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It has been a long time since my last post. I hope to get back into regularly posting once or twice a week. This project has been on hold since starting another project that dominated my life. I recently built a MAME Arcade Cabinet from scratch. (Pictures can be seen below)

Let’s jump right back in. We need a way to see instructions executing from memory. We need an I/O device.

To handle writing to an I/O device at some address the opcode ‘OUT’ can be used. For example in this small snippet of code we add a value to the accumulator ‘A’ and will keep writing the data that is in the accumulator ‘A’ to the device at address ‘0’.

start:
      ld a, 0BH
loop:
      out (0), a
      jp loop

What is the output device though, and how do we address it? Normally we could hook up a device to the Z80’s address bus, and send data to specific registers in that device by using the ‘OUT’ opcode, but in our case we will use LEDs, and just monitor the data that would have gone to the device. The address to send data to doesn’t matter because there is no addressable device so we will just output to device address ‘0’ for simplicity.

The ‘OUT’ opcode doesn’t just handle the data to send and the address of the device to go to, it also manipulates the Z80’s write control signal (WR PIN 22). When the Z80 is writing to an output device it asserts the WR pin, which tells the device that it is writing time. Using an octal latch we can capture this ‘write’ to the device, and see the data latched by using LEDs. The Z80 also asserts the IOREQ control signal (PIN 20), but we will not need this signal since there is no actual addressable device.

Since our assembly program is so small we will not need to address the entire ROM’s memory space. I limited my addressing to A0->A7, the first 8-bits, which is 2^8 or 256 address locations which are more than enough for our test. The rest of the address lines (A7->A15) need to be connected to ground and not left floating, otherwise you will start accessing bogus addresses as the floating address pins float up and down.

To monitor the address bus, data bus, and output I used the same module as I did in the Z80 Test Circuit. The address and data bus may start acting up since the LEDs introduce unwanted load on these lines to drive the module. I didn’t have any issue with a loading effect, but you might.

Below is the realized schematic for the Z80 ROM test circuit. You will notice I did not include the stepping circuit because the wiring becomes overwhelming with it included, and with such a small assembly program test, it did not seem worth it. Notice that the octal latch’s clock input (74LS373 PIN 11) is active-high while the Z80’s Write Enable pin (WR PIN 22) is active-low. You need to invert the WR pins output by either using my NPN transistor (2N3904) inverter solution as seen in the schematic, or you could use a 7404 Hex inverter. Using the 7404 is overkill for just one inversion however. Z80RTAll Files from this project can be downloaded from my GitHub Repository,

 Z80 Project Repository

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About Matt Cook

Computer Engineer
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